Nonvolatitle memory array and method for operating thereof

ABSTRACT

A mixed nonvolatile memory array. In the mixed nonvolatile memory array, each nonvolatile memory cell has at least one depletion mode memory cell. The depletion mode region is composed of a gate structure and a doped region. Since the thickness of the doped region is relatively thin, a voltage is applied on the gate structure to invert the conductive type of the doped region under the gate structure. Meanwhile, a bias is applied at both terminals of the doped region so as to control the operation of the depletion mode memory cell. In addition, each nonvolatile memory cell of the mixed nonvolatile memory array further comprises an enhanced mode memory cell. Therefore, each nonvolatile memory cell provides at least four carrier storage spaces so that the numbers of bits storing in a unit memory device is increased.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan applicationserial no. 95121186, filed on Jun. 14, 2006. All disclosure of theTaiwan application is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates to a nonvolatile memory array and methodfor operating the same. More particularly, the present invention relatesto a mixed nonvolatile memory array and method for operating the same.

2. Description of Related Art

Among the various types of non-volatile memory products, electricallyerasable programmable read only memory (EEPROM) is a memory device thathas been widely used inside personal computer systems and electronequipment. Data can be stored, read out or erased from the EEPROM manytimes and stored data are retained even after power supplying thedevices is cut off.

Typically, the floating gates and the control gates of the EEPROMnon-volatile memory are fabricated using doped polysilicon. When data isprogrammed into the memory, the electrons injected into the floatinggate will be evenly distributed throughout the entire polysiliconfloating gate layer. However, if the tunneling oxide layer underneaththe polysilicon gate contains some defects, a leakage current maydevelop leading to possible reliability problems in the device.

To prevent problems in operating the EEPROM due to leakage current, theconventional method is to use a charge-trapping layer instead of thepolysilicon floating gate. The charge-trapping layer is fabricated usingsilicon nitride, for example. In general, the silicon nitridecharge-trapping layer is sandwiched between a silicon oxide layer on topand another silicon oxide layer below to form an oxide/nitride/oxide(ONO) composite dielectric layer within a stack gate structure. AnEEPROM having this type of stack gate structure is known as a nitrideread-only-memory.

However, in the conventional technique, after the gate structure isformed, an ion implantation process is performed to form source/drainregion in a portion of the substrate exposed by the gate structure.Hence, the production cost is increased beside the addition of one moreion implantation process. Furthermore, in a two-time-feature-size squareregion, the unit memory device only provides two carrier storage space.

Hence, it is important to find a method capable of increasing thecarrier storage density in the unit nonvolatile memory device andreducing the cost for manufacturing the nonvolatile memory device.

SUMMARY OF THE INVENTION

Accordingly, at least one objective of the present invention is toprovide a nonvolatile memory cell. In the present invention, the nitridelayer in the oxide/nitride/oxide layer is used as a carrier trappingelement. Furthermore, a doped region with a relatively small thicknessis used as a source/drain region and the channel region under the gatestructure. Hence, by applying a voltage on the gate structure and a biason the terminals of the doped regions, the channel under the gatestructure can be well controlled to perform the operations such asprogramming, reading and erasing process. In addition, everytwo-feature-size square region possesses at least two carrier storagespaces.

The present invention further provides a mixed nonvolatile memory array.Since every mixed nonvolatile memory cell of the nonvolatile memoryarray comprises a depletion mode memory cell and an enhanced mode memorycell, it can provide at least at least four carrier storage spaces inevery two-feature-size square region. By comparing with the conventionalnitride read-only memory, the mixed nonvolatile memory array of thepresent invention does not need a buried diffusion oxide layerstructure, and the oxide/nitride/oxide layer under the gate iscompletely remained.

The present invention provides a method for operating the mixednonvolatile memory array capable of controlling the depletion modememory cell of the memory cell of the mixed nonvolatile memory array byapplying a voltage on the gate structure of the memory cell and applyinga bias on the doped region of the memory cell.

To achieve these and other advantages and in accordance with the purposeof the invention, as embodied and broadly described herein, theinvention provides a nonvolatile memory cell, the so-called depletionmode memory cell, comprising a substrate, a doped region and a gatestructure. The doped region is located in the substrate, wherein thedoped region has a conductive type and the doped region extends from atop surface of the substrate toward to a bottom of the substrate. Thegate structure located on the substrate and across the doped regioncomprises a multi-carrier storage element on the doped region and a gateon the multi-carrier storage element. Further, the multi-carrier storageelement comprises at least two carrier storage spaces including a firstcarrier storage space and a second carrier storage space, wherein thefirst carrier storage space and the second carrier storage space arelocated at each side of the multi-carrier storage element adjacent tothe doped region respectively.

In the non-volatile memory cell according to one embodiment of thepresent invention, during a programming process is performed on thenonvolatile memory cell, the doped region further comprises a firstinversion region in a portion of the doped region covered by the gatestructure, wherein the conductive type of the first inversion region isdifferent from that of the doped region. Furthermore, during a readingprocess is performed on the nonvolatile memory cell: when the firststorage space of the multi-carrier storage element stores at least onecarrier, the doped region further comprises a second inversion regionlocated in a portion of the doped region covered by a portion of thegate structure other than the first carrier storage space.Alternatively, when there is no carrier stored in both of the firststorage space and the second storage space, the doped region has a thirdinversion region located in a portion of the doped region covered by thegate structure. Further, the second inversion region and the thirdinversion region possess the same conductive type and the conductivetypes of the second inversion region and the third inversion region aredifferent from the conductive type of the doped region. Also, during anerasing process is performed on the nonvolatile memory cell, the dopedregion has a fourth inversion region covered by the gate structure,wherein the conductive type of the fourth inversion region is differentfrom that of the doped region.

In the non-volatile memory cell according to one embodiment of thepresent invention, the a thickness of the doped region is of about 200angstroms. Also, the multi-carrier storage element comprises anoxide/nitride/oxide layer. Moreover, there is at least one nonvolatilememory cell in a two-feature-size square region and a gate pitch size ofthe gate structure is smaller than a feature size.

In the present invention, since the silicon nitride layer of the siliconoxide/silicon nitride/silicon oxide layer is served as a carriertrapping element and the doped region with a relatively small thicknessis used as source/drain region and the channel region between thesource/drain regions can be controlled by applying voltages on the gatestructure and the source/drain region so as to operate the nonvolatilememory cell, the manufacturing method is relatively simple and the costis decreased as well.

The present invention also provides a mixed nonvolatile memory arrayhaving a plurality of mixed type memory cell. The mixed nonvolatilememory array comprises a substrate, at least two doped region, at leastone gate structure. The substrate possesses a first conductive type. Thedoped regions includes a first doped region and a second doped region,wherein the first doped region and the second doped region extend from atop surface of the substrate toward to a bottom of the substrate, thefirst doped region and the second doped region are parallel to eachother and the first doped region and the second doped region possesses asecond conductive type. Furthermore, the gate structure is located onthe substrate and across the doped regions and possesses several carrierstorage spaces. The gate structure, the first doped region and thesecond doped region together form a mixed type memory cell comprising anenhanced mode memory cell and a depletion mode memory cell. The enhancedmode memory cell is composed of the gate structure, a portion of thefirst doped region covered by the gate structure and a portion of thesecond doped region covered by the gate structure. Moreover, thedepletion mode memory cell is composed of the first doped region and thegate structure.

In the mixed nonvolatile memory array according to one preferredembodiment of the present invention, during a programming process isperformed on the depletion mode memory cell, the first doped region hasa first inversion region located in a portion of the first doped regioncovered by the gate structure and the conductive type of the firstinversion region is different from that of the first doped region.During a reading process is performed on the depletion mode memory cell:when the depletion mode memory cell is at a carrier storage state, thefirst doped region possesses a second inversion region covered by aportion of the gate structure other than the carrier storage spacesstoring at least one carrier and the conductive type of the secondinversion region is different from that of the first doped region.Alternatively, when the depletion mode memory cell is at a non-carrierstorage state, the first doped region has a third inversion regioncovered by the gate structure and the conductive type of the thirdinversion region is different from that of the first doped region. Also,during an erasing process is performed on the depletion mode memorycell, the first doped region has a fourth inversion region covered bythe gate structure and the conductive type of the fourth inversionregion is different from that of the first doped region.

In the mixed nonvolatile memory array according to one preferredembodiment of the present invention, the a thickness of each of thedoped regions is of about 200 angstroms. When the first conductive typeis P type, the second conductive type is N type; when the firstconductive type is N type, the second conductive type is P type.Moreover, the gate structure comprises a multi-carrier storage elementlocated on the substrate and a gate located on the multi-carrier storageelement. Further, the multi-carrier storage element includes anoxide/nitride/oxide layer. Also, the enhanced mode memory cell comprisesa first carrier storage space and a second carrier storage space locatedat a portion of the gate structure between the first doped region andthe second doped region, wherein the first carrier storage space isadjacent to the first doped region and the second carrier storage spaceis adjacent to the second doped region. The depletion mode memory cellcomprises a third carrier storage space and a fourth carrier storagespace located in a portion of the gate structure covering the firstdoped region. Furthermore, there is at least one mixed type memory cellin a two-feature-size square region and a gate pitch size of the gatestructure is smaller than a feature size.

For each memory cell of the present invention, there are a depletionmode memory cell and an enhanced mode memory cell. Hence, the density ofthe carrier storage space is increased. That is, for each 4F² region,there are at least four carrier storage spaces. By comparing with theconventional nitride read-only memory, the mixed nonvolatile memoryarray of the present invention does not need a buried diffusion oxidelayer structure, and the oxide/nitride/oxide layer under the gate iscompletely remained.

The present invention further provides a method for programming a mixednonvolatile memory array having a plurality of mixed memory cells,wherein each mixed memory cell includes a first doped region of a secondconductive type and a second doped region of the second conductive typelocated in a substrate of a first conductive type and parallel to andadjacent to each other. Each memory cell further includes a gatestructure located on the substrate and across the first doped region andthe second doped region. The first doped region and the gate structuretogether form a depletion mode memory cell and the first doped region,the second doped region and the first gate structure together form anenhanced mode memory cell. The method comprises steps of applying afirst voltage on the gate structure to turn on a channel region in thesubstrate under the gate structure between the first doped region andthe second doped region and applying a first bias on the first dopedregion and the second doped region to inject a plurality of electronsinto the gate structures in a way of channel hot carrier during theenhanced mode memory cell is programmed. Further, during the depletionmode memory cell is programmed, a second voltage is applied on the gatestructure to invert a conductive type of a portion of the first dopedregion under the gate structure from the second conductive type into thefirst conductive type and a second bias is applied on the first dopedregion to inject a plurality of holes into the gate structures in a wayof band-to-band tunneling hot carrier.

In programming method according to one embodiment of the presentinvention, a thickness of the first doped region is of about 200angstroms and a thickness of the second doped region is of about 200angstroms. When the first conductive type is P type and the secondconductive type is N type, the channel hot carrier includes a channelhot electron process and the band-to-band tunneling hot carrier includesa band-to-band tunneling hot hole process. Also, the gate structurecomprises a multi-carrier storage element located on the substrate and agate located on the multi-carrier storage element. The multi-carrierstorage element includes an oxide/nitride/oxide layer.

The present invention further provides a method for reading a mixednonvolatile memory array having a plurality of mixed memory cells,wherein each mixed memory cell includes a first doped region of a secondconductive type and a second doped region of the second conductive typelocated in a substrate of a first conductive type and parallel to andadjacent to each other. Each memory cell further includes a gatestructure located on the substrate and across the first doped region andthe second doped region. The first doped region and the gate structuretogether form a depletion mode memory cell and the first doped region,the second doped region and the first gate structure together form anenhanced mode memory cell. The method comprises steps of applying afirst voltage on the gate structure to turn on a channel region in thesubstrate under the gate structure between the first doped region andthe second doped region and applying a first bias between the firstdoped region and the second doped region to read the enhanced modememory cell in a way of reverse read during the enhanced mode memorycell is read. Furthermore, during the depletion mode memory cell isread, a second voltage is applied on the gate structure to invert aconductive type of a portion of the first doped region under the gatestructure from the second conductive type into the first conductive typeand applying a second bias on the first doped region to read thedepletion mode in the way of reverse read.

In the reading method according to one embodiment of the presentinvention, a thickness of the first doped region is of about 200angstroms and a thickness of the second doped region is of about 200angstroms. In addition, the gate structure comprises a multi-carrierstorage element located on the substrate and a gate located on themulti-carrier storage element, wherein the multi-carrier storage elementincludes an oxide/nitride/oxide layer.

The present invention further provides a method for erasing a mixednonvolatile memory array having a plurality of mixed memory cells,wherein each memory cell includes a first doped region of a secondconductive type and a second doped region of the second conductive typelocated in a substrate of a first conductive type and parallel to andadjacent to each other. Each memory cell further includes a gatestructure located on the substrate and across the first doped region andthe second doped region. The first doped region and the gate structuretogether form a depletion mode memory cell and the first doped region,the second doped region and the first gate structure together form anenhanced mode memory cell. The method comprises steps of applying afirst voltage on the gate structure and grounding the first doped regionand the second doped region to erase the enhanced mode memory cell in away of Flowler-Nordheim tunneling effect during the enhanced mode memorycell is erased. Furthermore, a second voltage is applied on the gatestructure and grounding the first doped region to erase the depletionmode in the way of Flowler-Nordheim tunneling effect during thedepletion mode memory cell is erased. When the enhanced mode memory celland the depletion mode memory cell are erased at the same time, thefirst voltage is equal to the second voltage.

In the erasing method according to one embodiment of the presentinvention, a thickness of the first doped region is of about 200angstroms and a thickness of the second doped region is of about 200angstroms. In addition, the gate structure comprises a multi-carrierstorage element located on the substrate and a gate located on themulti-carrier storage element, wherein the multi-carrier storage elementincludes an oxide/nitride/oxide layer.

Since the oxide/nitride/oxide layer is used as a carrier trappingelement and the doped region with a relatively small thickness is usedas source/drain region and the channel region between the source/drainregions, the manufacturing method is relatively simple and the cost isdecreased as well. Furthermore, there are at least four carrier storagespaces in a two-feature size square region so that the carrier storagedensity is increased. By comparing with the conventional nitrideread-only memory, the mixed nonvolatile memory array of the presentinvention does not need a buried diffusion oxide layer structure, andthe oxide/nitride/oxide layer under the gate is completely remained.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary, and are intended toprovide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1 is a top view showing a mixed nonvolatile memory array accordingto one embodiment of the present invention.

FIG. 2 is a cross-sectional view along a line 2-2 of a mixed nonvolatilememory array according to one embodiment of the present invention.

FIG. 3 is a cross-sectional view along a line 3-3 of a mixed nonvolatilememory array according to one embodiment of the present invention.

FIG. 4A is a cross-sectional view a depletion mode memory cell of amixed nonvolatile memory array during a programming process is performedon the depletion mode memory cell according to one embodiment of thepresent invention.

FIG. 4B is a cross-sectional view a depletion mode memory cell of amixed nonvolatile memory array during a reading process is performed onthe depletion mode memory cell according to one embodiment of thepresent invention.

FIG. 4C is a cross-sectional view a depletion mode memory cell of amixed nonvolatile memory array during an erasing process is performed onthe depletion mode memory cell according to one embodiment of thepresent invention.

FIG. 5A is a cross-sectional view an enhanced mode memory cell of amixed nonvolatile memory array during a programming process is performedon the enhanced mode memory cell according to one embodiment of thepresent invention.

FIG. 5B is a cross-sectional view an enhanced mode memory cell of amixed nonvolatile memory array during a reading process is performed onthe enhanced mode memory cell according to one embodiment of the presentinvention.

FIG. 5C is a cross-sectional view an enhanced mode memory cell of amixed nonvolatile memory array during an erasing process is performed onthe enhanced mode memory cell according to one embodiment of the presentinvention.

FIG. 6 is top view showing a mixed nonvolatile memory array according toanother embodiment of the present invention.

FIG. 7 is top view showing a mixed nonvolatile memory array according tothe other embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 is a top view showing a mixed nonvolatile memory array accordingto one embodiment of the present invention. FIG. 2 is a cross-sectionalview along a line 2-2 of a mixed nonvolatile memory array according toone embodiment of the present invention. FIG. 3 is a cross-sectionalview along a line 3-3 of a mixed nonvolatile memory array according toone embodiment of the present invention. As shown in FIGS. 1, 2 and 3,at least two parallel doped regions 102 are positioned in a substrate100. The doped regions 102 include a first doped region 102 a and asecond doped region 102 b. The substrate 100 can be a substrate having afirst conductive type or a silicon-on-insulator substrate.

In addition, the doped regions 102 including the first doped region 102a and the second doped region 102 b have a second conductive type. Thedoped regions 102 extend from a top surface of the substrate 100 towardto a bottom of the substrate 100. The thickness of the doped regions 102can be about 200 angstroms, for example. Furthermore, the doped regions102 are separated from each other. Moreover, the doped regions 102 canbe, for example, buried bit lines. Further, when the first conductivetype is P type, the second conductive type is N type; when the firstconductive type is N type, the second conductive type is P type.

As shown in FIGS. 1, 2 and 3, at least one gate structure 104 comprisinga first gate structure 104 a and a second gate structure 104 b ispositioned on the substrate 100 and across the doped regions 102. Thefirst gate structure 104 a and the second gate structure 104 b areparallel to each other and each gate structure 104 includes amulti-carrier storage element 108 located on the substrate 100 and agate 110 located on the multi-carrier storage element 108. Moreover, themulti-carrier storage element 108 can be, for example, anoxide/nitride/oxide layer which is a stacked layer formed by stacking anoxide layer 112, a nitride layer 114 and an oxide layer 116on thesubstrate 100 sequentially. Further, the nitride layer 114 is used as anelectron or hole trapping element in the operations of the nonvolatilememory array.

As shown in FIG. 1, a two-feature-size square (4F²) region 106 iscircled by bold-dotted line, wherein the feature size is half of asmallest device pitch. In the nonvolatile memory array of the presentembodiment of the invention, the gate pitch of the gate structure issmaller than or equal to double feature size. Furthermore, the mixedtype nonvolatile memory array of the present embodiment possesses aplurality of 4F² regions 106 and each 4F² region 106 includes at leastone nonvolatile memory cell.

In addition, each nonvolatile memory cell includes at least onedepletion mode memory cell. As shown in FIG. 2, taking a nonvolatilememory cell in the 4F² region 106 as an example, the depletion modememory cell is composed of the first doped region 102 a and the firstgate structure 104 a. Also, as shown in FIG. 1, the depletion modememory cell composed of the first doped region 102 a and the first gatestructure 104 comprises at least a third carrier storage space 114 a anda fourth carrier storage space 114 b located at both sides of themulti-carrier storage element 108 and adjacent to the first doped region102 a respectively.

Moreover, every nonvolatile memory cell further comprises an enhancedmode memory cell. As shown in FIG. 3, taking a nonvolatile memory cellin the 4F² region 106 as an example, the enhanced mode memory cell iscomposed of the first gate structure 104 a, a portion of the first dopedregion 102 a covered by the first gate structure 104 a and a portion ofthe second doped region 102 b covered by the first gate structure 104 a.

Therefore, when a nonvolatile memory cell comprises both an enhancedmode memory cell and a depletion mode memory cell, the nonvolatilememory cell is a mixed type nonvolatile memory cell. By comparing withthe conventional nitride read-only memory, the aforementioned mixednonvolatile memory array does not need a buried diffusion oxide layerstructure, and the oxide/nitride/oxide layer under the gate is remained.That is, there is no conventional buried diffusion oxide layer structureabove the substrate 100 and the gate structure 104 possesses a completemulti-carrier storage element 108.

FIG. 4A is a cross-sectional view a depletion mode memory cell of amixed nonvolatile memory array during a programming process is performedon the depletion mode memory cell according to one embodiment of thepresent invention. As shown in FIGS. 1 and 2, when there is no operationis performed on the depletion mode memory cell of a nonvolatile memorycell in the 4F² region 106, the channel region in the substrate 100under the first gate structure 104 a is in a turn on situation normally.Referring to FIG. 1 together with FIG. 4A, during the depletion modememory cell of the nonvolatile memory cell is programmed, a voltage isapplied on the first gate structure 104 a to invert a portion of thefirst doped region 102 a having the second conductive type and coveredby the first gate structure 104 a into a doped region 118 a, which isthe inversion region 118 a, with the first conductive type. That is, thechannel region in the substrate 100 under the first gate structure 104 ais turned off. Simultaneously, a bias is applied on the first dopedregion 102 a to program the depletion mode memory cell.

Preferably, when the first doped region 102 a is an N type doped region,a second voltage is applied on the first gate structure 104 a to invertthe portion of the doped region 102 a under the first gate structure 104a into the doped region 11 8 a with P conductive type, wherein thesecond voltage is of about −7 volt. Meanwhile, a second bias is appliedon an A terminal and a B terminal of the first doped region 102 a. Thesecond bias applied on the A terminal and the B terminal of the firstdoped region 102 a can be accomplished by applying a 5 volt on the Aterminal and grounding the B terminal. By applying the second bias onthe first doped region 102 a, a programming process in a way ofband-to-band tunneling hot carrier, such as the band-to-band tunnelinghot hole process, is triggered so as to inject holes from the firstdoped region 102 a into a third carrier storage space 114 a in a portionof the multi-carrier storage element 108 in the first gate structure 104a near to the A terminal. Hence, the threshold voltage at the thirdcarrier storage space 114 a is decreased from −2 volt to −5 volt. On theother hand, when the second voltage applied on the first gate structure104 a is fixed, the A terminal is grounded and a 5 volt is applied onthe B terminal, the programming process in a way of band-to-bandtunneling hot hole is triggered to inject holes from the first dopedregion 102 a into a fourth carrier storage space 114 b in a portion ofthe multi-carrier storage element 108 in the first gate structure 104 anear to the B terminal. Therefore, the threshold voltage at the fourthcarrier storage space 114 b is decreased from −2 volt to −5 volt.Although the programming process in a way of band-to-band tunneling hothole is recited above, the other programming process can be also appliedto program the depletion mode memory cell by applying proper voltages onthe first gate structure 104 a and the first doped region 102 a.

FIG. 4B is a cross-sectional view a depletion mode memory cell of amixed nonvolatile memory array during a reading process is performed onthe depletion mode memory cell according to one embodiment of thepresent invention. Referring to FIG. 1 together with FIG. 4B, during areading process is performed on the depletion mode memory cell havingthe third carrier storage space 114 a storing holes 114 a′, a voltage isapplied on the first gate structure 104 a. Therefore, a portion of thefirst doped region 102 a directly under the third carrier storage space114 a and a portion of the first doped region 102 a exposed by the firstgate structure 104 a still possess the second conductive type but therest portion of the first doped region 102 a is converted into a dopedregion 118 b, which is an inversion region, with the first conductivetype. In other words, when this depletion mode memory cell is at acarrier storage state, the so-called on state, the conductive type ofthe portion of the first doped region 102 a right under the first gatestructure 104 a is inverted from the second conductive type into thefirst conductive type. That is, an inversion region is formed in thefirst doped region right under a portion of the first gate structure. Onthe other words, the channel region in the substrate 100 under the firstgate structure 104 a is partially turned off. Simultaneously, a bias isapplied on the first doped region 102 a to read the depletion modememory cell.

Preferably, when the first doped region 102 a is an N type doped region,a third voltage is applied on the first gate structure 104 a to invertthe portion of the doped region 102 a under the first gate structure 104a into the doped region 118 a with P conductive type, wherein the thirdvoltage can be in a range from −2 volt to −5 volt and the preferredvalue of the third voltage is of about −3 volt. Meanwhile, a bias isapplied on the A terminal and the B terminal of the first doped region102 a. The bias applied on the A terminal and the B terminal of thefirst doped region 102 a can be accomplished by applying a 2 volt on theB terminal and grounding the A terminal. By applying the bias on thefirst doped region 102 a, a reading process in a way of reverse read istriggered to read the third carrier storage space 114 a′ of thisdepletion mode memory cell. Although the reading process in a way ofreverse read is recited above, the other reading process such as forwardreading process can be also applied to read the depletion mode memorycell by applying proper voltages on the first gate structure 104 a andthe first doped region 102 a.

Alternatively, under the circumstance that there is no carrier stored inthe multi-carrier storage element, during a reading process is performedon the depletion mode memory cell, by applying a voltage on the gatestructure, the conductive type of the portion of the doped regioncovered by the gate structure is converted from the second conductivetype into the first conductive type. That is, an inversion region isformed in the first doped region 102 a right under the first gatestructure. On the other words, under the situation that the depletionmode memory cell is at a non-carrier storage state, the so-called offstate, the channel region in the substrate under the first gatestructure is totally turned off during the reading process is performedon the depletion mode memory cell.

FIG. 4C is a cross-sectional view a depletion mode memory cell of amixed nonvolatile memory array during an erasing process is performed onthe depletion mode memory cell according to one embodiment of thepresent invention. Referring to FIG. 1 together with FIG. 4C, during anerasing process is performed on the depletion mode memory cell, avoltage is applied on the first gate structure 104 a and both the Aterminal and the B terminal of the first doped region 102 a aregrounded.

Preferably, when the first doped region 102 a is an N type doped region,a fourth voltage is applied on the first gate structure 104 a and boththe A terminal and the B terminal of the doped region 102 a aregrounded, wherein the fourth voltage can be −20. By applying the fourthvoltage on the first gate structure 104 a and grounding the first dopedregion 102 a, an erasing process in a way of Fowler-Nordheim tunnelingeffect is triggered. Hence, the threshold voltage of the depletion modememory cell is increased from −5 volt to −2 volt. Notably, theconductive type of the portion of the first doped region 102 covered bythe first gate structure 104 a is inverted from the second conductivetype into the first conductive type by applying the fourth voltage onthe first gate structure 104 a. Although the erasing process in a way ofFowler-Nordheim tunneling effect is recited above, the other erasingprocess can be also applied on the depletion mode memory cell byapplying proper voltages on the first gate structure 104 a and the firstdoped region 102 a.

FIG. 5A is a cross-sectional view a enhanced mode memory cell of a mixednonvolatile memory array during a programming process is performed onthe enhanced mode memory cell according to one embodiment of the presentinvention. As shown in FIGS. 1 and 3, when there is no operation isperformed on the enhanced mode memory cell of a nonvolatile memory cellin the 4F² region 106, the channel region in the substrate 100 under thefirst gate structure 104 a between the first doped region 102 a and thesecond doped region 102 b is in a turn off situation normally. That is,the conductive type of the channel region is the first conductive type.Referring to FIG. 1 together with FIG. 5A, during the enhanced modememory cell of the nonvolatile memory cell is programmed, a voltage isapplied on the first gate structure 104 a to invert the channel regionhaving the first conductive type into a channel region 120 with thesecond conductive type. That is, the channel region in the substrate 100under the first gate structure 104 a between the first doped region 102a and the second doped region 102 b is turned on. Simultaneously, a biasis applied between the first doped region 102 a and the second dopedregion 102 b to program the enhanced mode memory cell.

Preferably, when the first doped region 102 a and the second dopedregion 102 a are both the N type doped regions, a first voltage of about12 volt is applied on the first gate structure 104 a, a fifth voltage ofabout 5 volt is applied on the first doped region 102 a and a sixthvoltage of about 0 volt is applied on the second doped region 102 b.Therefore, a programming process in a way of channel hot carrier, suchas a channel hot electron process, is triggered so as to injectelectrons from the second doped region 102 b (i.e. source region) into asecond carrier storage space 114 d in a portion of the multi-carrierstorage element 108 in the first gate structure 104 a between the firstdoped region 102 a and the second doped region 102 b and near the firstdoped region 102 a (i.e. drain region). Hence, the threshold voltage atthe second carrier storage space 114 d is increased from 6 volt to 9volt. On the other hand, when the first voltage applied on the firstgate structure 104 a is fixed, the fifth voltage is of about 0 volt andthe sixth voltage is of about 5 volt, the programming process in a wayof channel hot electron is triggered to inject electrons from the firstdoped region 102 a (i.e. source region) into a first carrier storagespace 114 c in a portion of the multi-carrier storage element 108 in thefirst gate structure 104 a between the first doped region 102 a and thesecond doped region 102 b and near the second doped region 102 b (i.e.drain region). Therefore, the threshold voltage at the first carrierstorage space 114 c is increased from 6 volt to 9 volt. Although theprogramming process in a way of channel hot electron is recited above,the other programming process can be also applied to program theenhanced mode memory cell by applying proper voltages on the first gatestructure 104 a, the first doped region 102 a and the second dopedregion 102 b.

FIG. 5B is a cross-sectional view a enhanced mode memory cell of a mixednonvolatile memory array during a reading process is performed on theenhanced mode memory cell according to one embodiment of the presentinvention. Referring to FIG. 1 together with FIG. 5B, during a readingprocess is performed on the enhanced mode memory cell having the firstcarrier storage space 114 c storing electrons 114 c′, a voltage isapplied on the first gate structure 104 a to turn on a channel region122 with the second conductive type in the substrate 100 covered by thefirst gate structure 104 a between the first doped region 102 a and thesecond doped region 102 b, wherein the channel region 122 is near thetop surface of the substrate 100. Simultaneously, a bias is appliedbetween the first doped region 102 a and the second region 102 b to readthe enhanced mode memory cell.

Preferably, when the first doped region 102 a and the second dopedregion 102 a are both the N type doped regions, a seventh voltage, aeight voltage and a ninth voltage are applied on the first gatestructure 104 a, the first doped region 102 a and the second dopedregion 102 b respectively. Therefore, a reading process in a way ofreverse read is triggered to read the first carrier storage space 114 c′of this enhanced mode memory cell. Notably, the seventh voltage can bein a range from 6 volt to 9 volt and the preferred value of the seventhvoltage is of about 8 volt. Furthermore, the eighth voltage is of about2 volt and the ninth voltage is about of 0 volt. Although the readingprocess in a way of reverse read is recited above, the other readingprocess such as forward reading process can be also applied to read theenhanced mode memory cell by applying proper voltages on the first gatestructure 104 a, the first doped region 102 a and the second dopedregion 102 b.

FIG. 5C is a cross-sectional view a enhanced mode memory cell of a mixednonvolatile memory array during an erasing process is performed on theenhanced mode memory cell according to one embodiment of the presentinvention. Referring to FIG. 1 together with FIG. 5C, during an erasingprocess is performed on the enhanced mode memory cell, a voltage isapplied on the first gate structure 104 a and both the first dopedregion 102 a and the second doped region 102 b are grounded.

Preferably, when the first doped region 102 a and the second dopedregion 102 a are both the N type doped regions, a tenth voltage of about−20 volt is applied on the first gate structure 104 a and both the firstdoped region 102 a and the second doped region 102 b are grounded. Byapplying the tenth voltage on the first gate structure 104 a andgrounding the first doped region 102 a and the second doped region 102b, an erasing process in a way of Fowler-Nordheim tunneling effect istriggered. Hence, the threshold voltage of the enhanced mode memory cellis decreased from 9 volt to 6 volt. Although the erasing process in away of Fowler-Nordheim tunneling effect is recited above, the othererasing process can be also applied on the depletion mode memory cell byapplying proper voltages on the first gate structure 104 a, the firstdoped region 102 a and the second doped region 102 b.

In the embodiment described above, in every 4F² region 106, there is atleast one nonvolatile memory cell. As for each nonvolatile memory cell,there are at least one pair memory cell including a depletion modememory cell and an enhanced mode memory cell. In addition, each of thedepletion mode memory cell and the enhanced mode memory cell possessestwo carrier storage spaces. In other words, for each 4F² region 106, atleast four bits can be stored therein.

FIG. 6 is top view showing a mixed nonvolatile memory array according toanother embodiment of the present invention. As shown in FIG. 6, asimilar gate structures are inserted in the gate space between each twogate structures 104 in the above embodiment so that the gate pitch ofthe gate structure 604 is smaller than or equal to one feature size F.Therefore, for each 4F² region 606, there are at least two nonvolatilememory cells. That is, there are eight carrier storage spaces includingspace 614 a, space 614 b, space 614 c, space 614 d , space 614 e, space614 f, space 614 g and space 614 h in a 4F² region 606. Morespecifically, each 4F² region 606 can store at most 8 bits.

FIG. 7 is top view showing a mixed nonvolatile memory array according tothe other embodiment of the present invention. As shown in FIG. 7, whenthere are n (where n is not less than 3) gate structures within a 4F²region 706, there are 4n carrier storage spaces within the 4F² region706. That is, at most 4n bits can be stored in a single 4F² region 706.

Altogether, in the present invention, the oxide/nitride/oxide layer isused as a carrier trapping element and the doped region with therelatively small thickness is used as the source/drain regions and thechannel region of both the depletion mode memory cell and the enhancedmode memory cell. By applying the voltages on the gate structures andthe doped regions, the conductive type of a portion of the doped regionunder the gate structure is exchanged to either turn on or turn off thechannel between the source/drain regions. Therefore, there is no need toperform additional ion implantation process and gate patterning processso that the manufacturing cost is decreased. Furthermore, for eachmemory cell of the present invention, there are a depletion mode memorycell and an enhanced mode memory cell. Hence, the density of the carrierstorage space is increased. That is, for each 4F² region, there are atleast four carrier storage spaces. Moreover, when there are n gatestructures within a 4F² region, the number of the carrier storage spacesis greatly increased.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing descriptions, it is intended that the presentinvention covers modifications and variations of this invention if theyfall within the scope of the following claims and their equivalents.

1. A nonvolatile memory cell comprising: a substrate; a doped regionlocated in the substrate, wherein the doped region has a conductive typeand the doped region extends from a top surface of the substrate towardto a bottom of the substrate; and a gate structure located on thesubstrate and across the doped region, wherein the gate structurecomprises a multi-carrier storage element on the doped region and a gateon the multi-carrier storage element and the multi-carrier storageelement comprises at least two carrier storage spaces including a firstcarrier storage space and a second carrier storage space, wherein thefirst carrier storage space and the second carrier storage space arelocated adjacent to the multi-carrier storage element at both side ofthe doped region respectively and there is no buried diffusion oxidelayer structure over the substrate and the gate structure has completethe multi-carrier storage element.
 2. The nonvolatile memory cell ofclaim 1, wherein, during a programming process is performed on thenonvolatile memory cell, the doped region further comprises a firstinversion region in a portion of the doped region covered by the gatestructure.
 3. The nonvolatile memory cell of claim 2, wherein theconductive type of the first inversion region is different from that ofthe doped region.
 4. The nonvolatile memory cell of claim 1, wherein,during a reading process is performed on the nonvolatile memory cell:when the first storage space of the multi-carrier storage element storesat least one carrier, the doped region further comprises a secondinversion region located in a portion of the doped region covered by aportion of the gate structure other than the first carrier storagespace; and when there is no carrier stored in the multi-carrier storageelement, the doped region has a third inversion region located in aportion of the doped region covered by the gate structure.
 5. Thenonvolatile memory cell of claim 4, wherein the second inversion regionand the third inversion region possess the same conductive type and theconductive types of the second inversion region and the third inversionregion are different from the conductive type of the doped region. 6.The nonvolatile memory cell of claim 1, wherein, during an erasingprocess is performed on the nonvolatile memory cell, the doped regionhas a fourth inversion region in a portion of the doped region coveredby the gate structure.
 7. The nonvolatile memory cell of claim 6,wherein the conductive type of the fourth inversion region is differentfrom that of the doped region.
 8. The nonvolatile memory cell of claim1, wherein a thickness of the doped region is of about 200 angstroms. 9.The nonvolatile memory cell of claim 1, wherein the multi-carrierstorage element comprises an oxide/nitride/oxide layer.
 10. Thenonvolatile memory cell of claim 1, wherein there is at least onenonvolatile memory cell in a two-feature-size square region.
 11. Thenonvolatile memory cell of claim 1, wherein a gate pitch size of thegate structure is smaller than a feature size.
 12. A mixed nonvolatilememory array having a plurality of mixed type memory cell, comprising: asubstrate having a first conductive type, wherein the substratepossesses at least two doped regions including a first doped region anda second doped region, the first doped region and the second dopedregion extend from a top surface of the substrate toward to a bottom ofthe substrate, the first doped region and the second doped region areparallel to each other and the first doped region and the second dopedregion possesses a second conductive type; and at least a gate structurelocated on the substrate and across the doped regions and possessing aplurality of carrier storage spaces, wherein the gate structure, thefirst doped region and the second doped region together form a mixedtype memory cell and the mixed type memory cell comprises: an enhancedmode memory cell composed of the gate structure, a portion of the firstdoped region covered by the gate structure and a portion of the seconddoped region covered by the gate structure; and a depletion mode memorycell composed of the first doped region and the gate structure.
 13. Themixed nonvolatile memory array of claim 12, wherein, during aprogramming process is performed on the depletion mode memory cell, thefirst doped region has a first inversion region located in a portion ofthe first doped region covered by the gate structure and the conductivetype of the first inversion region is different from that of the firstdoped region.
 14. The mixed nonvolatile memory array of claim 12,wherein, during a reading process is performed on the depletion modememory cell: when the depletion mode memory cell is at a carrier storagestate, the first doped region possesses a second inversion regioncovered by a portion of the gate structure other than the carrierstorage spaces, which store at least one carrier, and the conductivetype of the second inversion region is different from that of the firstdoped region; and when the depletion mode memory cell is at anon-carrier storage state, the first doped region has a third inversionregion covered by the gate structure and the conductive type of thethird inversion region is different from that of the first doped region.15. The mixed nonvolatile memory array of claim 12, wherein, during anerasing process is performed on the depletion mode memory cell, thefirst doped region has a fourth inversion region covered by the gatestructure and the conductive type of the fourth inversion region isdifferent from that of the first doped region.
 16. The mixed nonvolatilememory array of claim 12, wherein a thickness of each of the dopedregions is of about 200 angstroms.
 17. The mixed nonvolatile memoryarray of claim 12, wherein when the first conductive type is P type, thesecond conductive type is N type; when the first conductive type is Ntype, the second conductive type is P type.
 18. The mixed nonvolatilememory array of claim 12, wherein the gate structure comprises amulti-carrier storage element located on the substrate and a gatelocated on the multi-carrier storage element.
 19. The mixed nonvolatilememory array of claim 18, wherein the multi-carrier storage elementincludes an oxide/nitride/oxide layer.
 20. The mixed nonvolatile memoryarray of claim 12, wherein the enhanced mode memory cell comprises afirst carrier storage space and a second carrier storage space locatedat a portion of the gate structure between the first doped region andthe second doped region, the first carrier storage space is adjacent tothe first doped region and the second carrier storage space is adjacentto the second doped region.
 21. The mixed nonvolatile memory array ofclaim 12, wherein the depletion mode memory cell comprises a thirdcarrier storage space and a fourth carrier storage space located in bothsides of the gate structure covering the first doped region and adjacentto the first doped region respectively.
 22. The mixed nonvolatile memoryarray of claim 12, wherein there is at least one mixed type memory cellin a two-feature-size square region.
 23. The mixed nonvolatile memoryarray of claim 12, wherein a gate pitch size of the gate structure issmaller than a feature size.
 24. The mixed nonvolatile memory array ofclaim 12, wherein the gate structure further comprises a completemulti-carrier storage element having the carrier storage spaces.
 25. Amethod for programming a nonvolatile memory array having a plurality ofmemory cells, wherein each memory cell includes a first doped region ofa second conductive type and a second doped region of the secondconductive type located in a substrate of a first conductive type andparallel to and adjacent to each other, each memory cell furtherincludes a gate structure located on the substrate and across the firstdoped region and the second doped region, the first doped region and thegate structure together form a depletion mode memory cell and the firstdoped region, the second doped region and the first gate structuretogether form an enhanced mode memory cell, and method comprising:during the enhanced mode memory cell is programmed, applying a firstvoltage on the gate structure to turn on a channel region having thesecond conductive type in the substrate under the gate structure betweenthe first doped region and the second doped region and applying a firstbias between the first doped region and the second doped region toinject a plurality of electrons into the gate structures in a way ofchannel hot carrier; and during the depletion mode memory cell isprogrammed, applying a second voltage on the gate structure to invert aconductive type of a portion of the first doped region under the gatestructure from the second conductive type into the first conductive typeand applying a second bias on the first doped region to inject aplurality of holes into the gate structures in a way of band-to-bandtunneling hot carrier.
 26. The method of claim 25, wherein a thicknessof the first doped region is of about 200 angstroms and a thickness ofthe second doped region is of about 200 angstroms.
 27. The method ofclaim 25, wherein when the first conductive type is P type and thesecond conductive type is N type, the channel hot carrier includes achannel hot electron process and the band-to-band tunneling hot carrierincludes a band-to-band tunneling hot hole process.
 28. The method ofclaim 25, wherein the gate structure comprises a multi-carrier storageelement located on the substrate and a gate located on the multi-carrierstorage element.
 29. The method of claim 28, wherein the multi-carrierstorage element includes an oxide/nitride/oxide layer.
 30. A method forreading a nonvolatile memory array having a plurality of memory cells,wherein each memory cell includes a first doped region of a secondconductive type and a second doped region of the second conductive typelocated in a substrate of a first conductive type and parallel to andadjacent to each other, each memory cell further includes a gatestructure located on the substrate and across the first doped region andthe second doped region, the first doped region and the gate structuretogether form a depletion mode memory cell and the first doped region,the second doped region and the first gate structure together form anenhanced mode memory cell, and method comprising: during the enhancedmode memory cell is read, applying a first voltage on the gate structureto turn on a channel region having the second conductive type in thesubstrate under the gate structure between the first doped region andthe second doped region and applying a first bias between the firstdoped region and the second doped region to read the enhanced modememory cell in a way of reverse read; and during the depletion modememory cell is read, applying a second voltage on the gate structure toinvert a conductive type of a portion of the first doped region underthe gate structure from the second conductive type into the firstconductive type and applying a second bias on the first doped region toread the depletion mode in the way of reverse read.
 31. The method ofclaim 30, wherein a thickness of the first doped region is of about 200angstroms and a thickness of the second doped region is of about 200angstroms.
 32. The method of claim 30, wherein the gate structurecomprises a multi-carrier storage element located on the substrate and agate located on the multi-carrier storage element.
 33. The method ofclaim 32, wherein the multi-carrier storage element includes anoxide/nitride/oxide layer.
 34. A method for erasing a nonvolatile memoryarray having a plurality of memory cells, wherein each memory cellincludes a first doped region of a second conductive type and a seconddoped region of the second conductive type located in a substrate of afirst conductive type and parallel to and adjacent to each other, eachmemory cell further includes a gate structure located on the substrateand across the first doped region and the second doped region, the firstdoped region and the gate structure together form a depletion modememory cell and the first doped region, the second doped region and thefirst gate structure together form an enhanced mode memory cell, andmethod comprising: during the enhanced mode memory cell is erased,applying a first voltage on the gate structure and grounding the firstdoped region and the second doped region to erase the enhanced modememory cell in a way of Flowler-Nordheim tunneling effect; and duringthe depletion mode memory cell is erased, applying a second voltage onthe gate structure and grounding the first doped region to erase thedepletion mode in the way of Flowler-Nordheim tunneling effect.
 35. Themethod of claim 34, wherein a thickness of the first doped region is ofabout 200 angstroms and a thickness of the second doped region is ofabout 200 angstroms.
 36. The method of claim 34, wherein the gatestructure comprises a multi-carrier storage element located on thesubstrate and a gate located on the multi-carrier storage element. 37.The method of claim 36, wherein the multi-carrier storage elementincludes an oxide/nitride/oxide layer.
 38. The method of claim 34,wherein, when the enhanced mode memory cell and the depletion modememory cell are erased at the same time, the first voltage is equal tothe second voltage.